Question 1. What Is Difference Between Latch And Flip-flop?
The most important distinction among latch and FF is that latches are level touchy at the same time as FF is area sensitive. They each require the usage of clock signal and are used in sequential good judgment. For a latch, the output tracks the input when the clock sign is excessive, so so long as the clock is good judgment 1, the output can alternate if the input also changes.
FF then again, will save the enter best whilst there's a rising/falling fringe of the clock. Latch is sensitive to system faults on permit pin, whereas turn-flop is immune to system defects. Latches take fewer gates (also less energy) to implement than turn-flops. Latches are quicker than flip-flops
Question 2. Given Only Two Xor Gates One Must Function As Buffer And Another As Inverter?
Tie one in all xor gates input to at least one it'll act as inverter.
Tie one in all xor gates enter to 0 it'll act as buffer.
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Question three. Difference Between Mealy And Moore State Machine?
A) Mealy and Moore fashions are the basic fashions of country machines. A nation device which makes use of only Entry Actions, in order that its output relies upon at the state, is known as a Moore model. A nation device which uses handiest Input Actions, so that the output relies upon at the nation and additionally on inputs, is referred to as a Mealy version. The models decided on will affect a layout but there are no general warning signs as to which model is higher. Choice of a version depends on the application, execution way (for instance, hardware systems are generally excellent found out as Moore fashions) and personal possibilities of a dressmaker or programmer
B) Mealy gadget has outputs that rely upon the country and input (for this reason, the FSM has the output written on edges) Moore gadget has outputs that rely on kingdom most effective (for this reason, the FSM has the output written inside the kingdom itself.
Advantage and Disadvantage
•In Mealy as the output variable is a characteristic both input and kingdom, adjustments of nation of the state variables can be not on time with admire to changes of signal stage inside the input variables, there are possibilities of system faults performing inside the output variables.
•Moore overcomes glitches as output depending on only states and now not the enter signal stage.
•All of the ideas may be carried out to Moore-version nation machines because any Moore kingdom device can be carried out as a Mealy nation machine, despite the fact that the speak is not genuine.
•Moore device: the outputs are homes of states themselves... Because of this that you get the output after the gadget reaches a specific country, or to get some output your gadget has to be taken to a kingdom which presents you the output. The outputs are held till you go to a few other nation Mealy system:
•Mealy machines give you outputs instantly, this is without delay upon receiving input, but the output is not held after that clock cycle.
Question 4. Difference Between One Hot And Binary Encoding?
Common classifications used to describe the state encoding of an FSM are Binary (or noticeably encoded) and One warm.
A binary-encoded FSM design handiest requires as many turn-flops as are had to uniquely encode the quantity of states in the state gadget. The actual quantity of flip-flops required is identical to the ceiling of the log-base-2 of the wide variety of states inside the FSM.A one warm FSM layout calls for a turn-flop for every kingdom inside the layout and handiest one flip-flop (the turn-flop representing the contemporary or "hot" country) is about at a time in a one hot FSM design.
For a state system with nine- 16 states, a binary FSM only calls for 4 turn-flops at the same time as a one hot FSM calls for a flip-flop for every nation within the layout FPGA providers often propose the use of a one warm country encoding fashion due to the fact turn-flops are considerable in an FPGA and the combinational common sense required to put into effect a one warm FSM layout is usually smaller than maximum binary encoding styles.
Since FPGA overall performance is commonly related to the combinational common sense length of the FPGA layout, one hot FSMs generally run quicker than a binary encoded FSM with larger combinational common sense blocks
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Question 5. How To Achieve 180 Degree Exact Phase Shift?
Never tell using inverter
a) DCM an in-built resource in maximum of FPGA can be configured to get 180 degree section shift.
B) BUFGDS this is differential signaling buffers which can be additionally built in resource of most of FPGA can be used.
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Question 6. What Is Significance Of Ras And Cas In Sdram?
SDRAM gets its deal with command in two deal with phrases. It uses a multiplex scheme to store enter pins. The first deal with phrase is latched into the DRAM chip with the row cope with strobe (RAS).
Following the RAS command is the column deal with strobe (CAS) for latching the second cope with word. Shortly after the RAS and CAS strobes, the saved records is valid for reading.
Question 7. Tell Some Of Applications Of Buffer?
a) They are used to introduce small delays.
B) They are used to dispose of pass talk prompted because of inter electrode capacitance because of near routing.
C) They are used to help excessive fan-out, e.G.: bufg
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Question eight. Give Two Ways Of Converting A Two Input Nand Gate To An Inverter?
a) Short the 2 inputs of the nand gate and observe the single enter to it.
B) Connect the output to one of the enter and the alternative to the input sign.
Question nine. Why Is Most Interrupts Active Low?
This answers why most indicators are lively low in case you recollect the transistor level of a module, energetic low means the capacitor within the output terminal gets charged or discharged based on low to high and excessive to low transition respectively. When it goes from high to low it relies upon on the pull down resistor that attracts it down and it is fantastically smooth for the output capacitance to discharge in preference to charging. Hence humans prefer the use of lively low alerts.
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Question 10. Design A Four-input Nand Gate Using Only Two-input Nand Gates.
Basically, you could tie the inputs of a NAND gate collectively to get an inverter.
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Question 11. What Will Happen If Contents Of Register Are Shifter Left, Right?
It is well known that during left shift all bits can be shifted left and LSB might be appended with zero and in right shift all bits could be shifted right and MSB could be appended with zero this is a truthful solution What is expected is in a left shift fee gets Multiplied with the aid of 2
e.G.: recollect 0000_1110=14 a left shift will make it 0001_110=28, it the equal style proper shift will Divide the fee by way of 2.
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Question 12. Given The Following Fifo And Rules, How Deep Does The Fifo Need To Be To Prevent Underflow Or Overflow?
1) frequency(clk_A) = frequency(clk_B) / four
2) period(en_B) = duration(clk_A) * a hundred
three) responsibility cycle(en_B) = 25%
Assume clk_B = 100MHz (10ns)
From (1), clk_A = 25MHz (40ns)
From (2), length(en_B) = 40ns * four hundred = 4000ns, but we simplest output for 1000ns,because of (3), so 3000ns of the enable we are doing no output paintings. Therefore, FIFO length = 3000ns/40ns = seventy five entries
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Question 13. Differences Between D-latch And D Flip-flop?
D-latch is stage touchy in which as turn-flop is edge touchy. Flip-flops are made up of latches.
Question 14. What Is A Multiplexer?
Is a combinational circuit that selects binary information from considered one of many enter strains and directs it to a unmarried output line.
(2n =>n). Where n is selection line.
Question 15. What Are Set Up Time & Hold Time Constraints? What Do They Signify? Which One Is Critical For Estimating Maximum Clock Frequency Of A Circuit?
Set up time is the amount of time the records ought to be strong before the application of the clock signal, in which as the hold time is the quantity of time the information ought to be strong after the application of the clock. Setup time indicates maximum delay constraints; maintain time is for minimal postpone constraints. Setup time is critical for organising the maximum clock frequency.
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Question sixteen. How Can You Convert An Sr Flip-flop To A Jk Flip-flop?
By giving the remarks we will convert, i.E. !Q=>S and Q=>R.Hence the S and R inputs will act as J and K respectively.
Question 17. How Can You Convert The Jk Flip-flop To A D Flip-flop?
By connecting the J enter to the K thru the inverter.
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Question 18. How Do You Detect If Two 8-bit Signals Are Same?
XOR each bits of A with B (for e.G. A  xor B ) and so on. The o/p of 8 xor gates is then given as i/p to an eight-i/p nor gate.
If o/p is 1 then A=B.
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Question 19. Convert D-ff Into Divide By 2. (now not Latch) What Is The Max Clock Frequency The Circuit Can Handle, Given The Following Information?
T_setup= 6nsT_hold = 2nS T_propagation = 10nS
Circuit: Connect Qbar to D and follow the clk at clk of DFF and take the O/P at Q. It offers freq/2. Max. Freq of operation: 1/ (propagation put off+setup time) = 1/16ns = sixty two.5 MHz
Question 20. 7 Bit Ring Counter's Initial State Is 0100010. After How Many Clock Cycles Will It Return To The Initial State?
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Question 21. Design All The Gates (no longer, And, Or, Nand, Nor, Xor, Xnor) Using 2:1 Multiplexer?
Using 2:1 Mux, (2 inputs, 1 output and a pick out line)
a) NOT :Give the input on the choose line and connect I0 to 1 & I1 to 0. So if A is 1, we can get I1 this is 0 at the O/P.
B) AND: Give input A on the choose line and 0 to I0 and B to I1. O/p is A & B
c) OR: Give enter A at the pick out line and 1 to I1 and B to I0. O/p can be A together
e) NOR: OR + NOT implementations together
f) XOR: A at the choose line B at I0 and ~B at I1. ~B may be obtained from (a)
g) XNOR: A on the choose line B at I1 and ~B at I0
Question 22. Design A Circuit That Calculates The Square Of A Number?
It must no longer use any multiplier circuits. It have to use Multiplexers and different good judgment?
See a pattern yet? To get the next square, all you need to do is upload the next abnormal number to the preceding rectangular which you discovered. See how 1,3,five,7 and in the end 9 are added. Wouldn’t this be a possible strategy to your query because it best will use a counter, multiplexer and more than one adders? It appears it might take n clock cycles to calculate square of n.
Question 23. N Number Of Xnor Gates Is Connected In Series Such That The N Inputs (a0, A1, A2......) Are Given In The Following Way: A0 & A1 To First Xnor Gate And A2 & O/p Of First Xnor To Second Xnor Gate And So On..... Nth Xnor Gates Output Is Final Output. How Does This Circuit Work? Explain In Detail?
If N=Odd, the circuit acts as even parity detector, i.E. The output will 1 if there are even variety of 1's inside the N input...This may also be referred to as as extraordinary parity generator in view that with this extra 1 as output the entire range of one's may be ODD. If N=Even, just the alternative, it is going to be Odd parity detector or Even Parity Generator.
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Question 24. What Is Race-round Problem? How Can You Rectify It?
The clock pulse that remains inside the 1 state at the same time as both J and K are equal to one will motive the output to complement again and repeat complementing till the pulse is going returned to zero, that is known as the race round hassle. To avoid this unwanted operation, the clock pulse need to have a time duration this is shorter than the propagation delay time of the F-F, this is restrictive so the alternative is master-slave or side-brought about production.
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Question 25. An Assembly Line Has 3 Fail Safe Sensors And One Emergency Shutdown Switch. The Line Should Keep Moving Unless Any Of The Following Conditions Arise:
(i) If the emergency switch is pressed
(ii) If the senor1 and sensor2 are activated on the same time.
(iii) If sensor 2 and sensor3 are activated on the equal time.
(iv) If all the sensors are activated at the equal time
suppose a combinational circuit for above case is to be carried out most effective with NAND Gates. How many minimal wide variety of two input NAND gates are required?
No of two-input NAND Gates required = 6 you may attempt the complete implementation.
Question 26. How Will You Implement A Full Subtractor From A Full Adder?
All the bits of subtrahend ought to be connected to the xor gate. Other input to the xor being one. The enter carry bit to the overall adder ought to be made 1. Then the entire adder works like a complete subtract.
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Question 27. What Is Difference Between Setup And Hold Time. The Interviewer Was Looking For One Specific Reason, And Its Really A Good Answer Too..The Hint Is Hold Time Doesn't Depend On Clock, Why Is It So...?
Setup violations are associated with two edges of clock, i imply you could range the clock frequency to accurate setup violation. But for keep time, you're only involved with one aspect and do now not basically rely upon clock frequency.
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Question 28. In A 3-bit Johnson's Counter What Are The Unused States?
2(electricity n)-2n is the only used to discover the unused states in Johnson counter.
So for a three-bit counter it's miles 8-6=2.Unused states=2. The 2 unused states are 010 and 101.
Question 29. What Is Difference Between Ram And Fifo?
FIFO does now not have cope with traces
Ram is used for storage cause where as FIFO is used for synchronization purpose i.E. While peripherals are running in distinct clock domain names then we will cross for FIFO.
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Question 30. Consider Two Similar Processors, One With A Clock Skew Of 100ps And Other With A Clock Skew Of 50ps. Which One Is Likely To Have More Power? Why?
Clock skew of 50ps is much more likely to have clock strength. This is due to the fact it's far possibly that low-skew processor has higher designed clock tree with extra effective and number of buffers and overheads to make skew higher.
Question 31. Is It Possible To Reduce Clock Skew To Zero? Explain Your Answer?
Even though there are clock layout techniques (H-tree) which can in idea reduce clock skew to zero with the aid of having the identical direction duration from each turn-flop from the pll, method variations in R and C throughout the chip will purpose clock skew in addition to a pure H-Tree scheme isn't always sensible (consumes an excessive amount of place).
Question 32. The Circle Can Rotate Clockwise And Back. Use Minimum Hardware To Build A Circuit To Indicate The Direction Of Rotating?
2 sensors are required to discover the route of rotating. They are placed like at the drawing. One of the m is attached to the data input of D flip-flop, and a 2d one - to the clock input. If the circle rotates the manner clock sensor sees the mild first at the same time as D input (second sensor) is zero - the output of the turn-flop equals 0, and if D input sensor "fires" first - the output of the flip-flop turns into excessive.
Question 33. You Have Two Counters Counting Upto 16, Built From Negedge Dff , First Circuit Is Synchronous And Second Is "ripple" (cascading), Which Circuit Has A Less Propagation Delay? Why?
The synchronous counter can have lesser put off because the enter to each flop is simply available earlier than the clock edge. Whereas the cascade counter will take long term because the output of one flop is used as clock to the alternative. So the postpone might be propagating. For E.G.: 16 country counter = four bit counter = four Flip flops Let 10ns be the put off of every flop The worst case postpone of ripple counter = 10 * four = 40ns The put off of synchronous counter = 10ns best.(Delay of one flop)
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Question 34. Difference Between Synchronous And Asynchronous Reset?
Synchronous reset logic will synthesize to smaller turn-flops, specifically if the reset is gated with the good judgment producing the dinput. But in the sort of case, the combinational logic gate count number grows, so the overall gate remember savings may not be that big. The clock works as a filter for small reset glitches; however, if those system defects arise close to the energetic clock aspect, the Flip-flop may want to move metastable. In a few designs, the reset need to be generated via a hard and fast of inner situations. A synchronous reset is usually recommended for these types of designs because it will clear out the common sense equation system defects among clocks.
Disadvantages of synchronous reset:
Problem with synchronous resets is that the synthesis device cannot effortlessly distinguish the reset signal from another facts sign. Synchronous resets can also need a pulse stretcher to guarantee a reset pulse width huge enough to ensure reset is present all through an lively fringe of the clock. When you have a gated clock to shop power, the clock can be disabled coincident with the declaration of reset. Only an asynchronous reset will work in this example, because the reset is probably eliminated previous to the resumption of the clock. Designs which are pushing the limit for records route timing, can't find the money for to have added gates and extra net delays inside the facts path because of common sense inserted to handle synchronous resets.
The largest hassle with asynchronous resets is the reset launch, also called reset removal. Using an asynchronous reset, the dressmaker is assured now not to have the reset added to the information course. Another benefit favoring asynchronous resets is that the circuit may be reset with or without a clock present.
Disadvantages of asynchronous reset: ensure that the discharge of the reset can arise within one clock duration. If the discharge of the reset occurred on or close to a clock aspect such that the flip-flops went metastable.
Question 35. Implement The Following Circuits:
(a) three input NAND gate the usage of min no of 2 enter NAND Gates
(b) three enter NOR gate the usage of min no of 2 input NOR Gates
(c) three enter XNOR gate using min no of 2 enter XNOR Gates
Assuming three inputs A,B,C?
3 enter NAND Connect:
a) A and B to the primary NAND gate
b) Output of first Nand gate is given to the two inputs of the second one NAND gate (this essentially realizes the inverter functionality)4
c) Output of 2nd NAND gate is given to the input of the third NAND gate, whose other enter is C ((A NAND B) NAND (A NAND B)) NAND C Thus, may be applied the use of 'three' 2-enter NAND gates. I wager this is the minimal number of gates that want to be used.