Question 1. Explain About Setup Time And Hold Time, What Will Happen If There Is Setup Time And Hold Tine Violation, How To Overcome This?
Set up time is the quantity of time earlier than the clock part that the input signal desires to be stable to guarantee it is standard properly at the clock area.
Hold time is the quantity of time after the clock facet that identical input signal needs to be held before changing it to make sure it's far sensed well on the clock edge.
Whenever there are setup and preserve time violations in any flipflop, it enters a nation wherein its output is unpredictable: this state is known as metastable country (quasi stable kingdom)? at the cease of metastable kingdom, the flipflop settles all the way down to either ‘1’ or ‘zero’. This whole manner is referred to as metastability.
Question 2. What Is Skew, What Are Problems Associated With It And How To Minimize It?
In circuit layout, clock skew is a phenomenon in synchronous circuits in which the clock signal (despatched from the clock circuit) arrives at one-of-a-kind components at distinct times.
This is normally because of causes. The first is a cloth flaw, which reasons a signal to travel faster or slower than expected. The 2d is distance: if the signal has to journey the complete length of a circuit, it will in all likelihood (relying at the circuit’s length) arrive at different components of the circuit at exceptional times. Clock skew can cause damage in two methods. Suppose that a common sense path travels through combinational good judgment from a source flipflop to a vacation spot flipflop. If the destination flipflop receives the clock tick later than the supply flipflop, and if the common sense path postpone is brief sufficient, then the facts signal may arrive on the destination flipflop earlier than the clock tick, destroying there the previous statistics that need to were clocked thru. This is called a maintain violation due to the fact the previous data isn't always held long sufficient on the vacation spot flipflop to be nicely clocked via. If the vacation spot flipflop receives the clock tick earlier than the source flipflop, then the records sign has that a great deal less time to attain the destination flipflop before the next clock tick. If it fails to achieve this, a setup violation takes place, socalled due to the fact the new facts become now not installation and solid earlier than the subsequent clock tick arrived. A keep violation is extra serious than a setup violation as it can not be fixed via growing the clock length.
Clock skew, if finished right, can also advantage a circuit. It can be intentionally brought to lower the clock length at which the circuit will function efficiently, and/or to boom the setup or maintain protection margins. The most useful set of clock delays is determined by using a linear program, in which a setup and a hold constraint appears for each common sense path. In this linear program, 0 clock skew is merely a viable factor.
Clock skew can be minimized by means of proper routing of clock signal (clock distribution tree) or placing variable put off buffer so that each one clock inputs arrive on the same time.
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Question 3. What Is Slack?
‘Slack’ is the amount of time you've got this is measured from when an event ‘truly happens’ and while it ‘have to happen’.. The term ‘definitely takes place’ can also be taken as being a anticipated time for whilst the event will ‘clearly take place’.
When something ‘ought to appear’ can also be called a ‘deadline’ so some other definition of slack will be the time from whilst some thing ‘in reality occurs’ (call this Tact) till the deadline (name this Tdead).
Slack = Tdead – Tact.
Negative slack implies that the ‘genuinely occur’ time is later than the ‘closing date’ time…in different words it’s too overdue and a timing violation….You have a timing problem that desires some attention.
Question four. What Is Glitch? What Causes It (explain With Waveform)? How To Overcome It?
The following parent indicates a synchronous alternative to the gated clock the usage of a statistics direction. The flipflop is clocked at each clock cycle and the facts route is controlled by an enable. When the allow is Low, the multiplexer feeds the output of the sign up back on itself. When the allow is High, new facts is fed to the flipflop and the check in changes its country.
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Question 5. Given Only Two Xor Gates One Must Function As Buffer And Another As Inverter?
Tie certainly one of xor gates enter to 1 it's going to act as inverter.
Tie considered one of xor gates input to 0 it'll act as buffer.
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Question 6. What Is Difference Between Latch And Flipflop?
The principal distinction between latch and FF is that latches are degree sensitive whilst FF are facet touchy. They both require the use of clock signal and are utilized in sequential good judgment. For a latch, the output tracks the enter whilst the clock sign is high, so so long as the clock is logic 1, the output can alternate if the input also adjustments. FF on the other hand, will shop the enter best whilst there is a rising/falling fringe of the clock.
Question 7. Difference Between Heap And Stack?
The Stack is more or much less accountable for retaining song of what’s executing in our code (or what’s been “called”). The Heap is extra or much less liable for keeping music of our items (our statistics, well… maximum of it – we’ll get to that later.).
Think of the Stack as a sequence of packing containers stacked one on top of the following. We keep track of what’s going on in our utility by using stacking every other container on top every time we call a way (known as a Frame). We can only use what’s within the top field on the stack. When we’re achieved with the pinnacle container (the technique is carried out executing) we throw it away and continue to use the stuff within the preceding field on the pinnacle of the stack. The Heap is similar besides that its cause is to preserve facts (no longer maintain song of execution most of the time) so something in our Heap may be accessed at any time. With the Heap, there are not any constraints as to what may be accessed like within the stack. The Heap is just like the heap of clean laundry on our mattress that we have no longer taken the time to position away yet – we are able to clutch what we want speedy. The Stack is like the stack of shoe packing containers inside the closet where we need to take off the pinnacle one to get to the one under it.
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Question eight. Difference Between Mealy And Moore State Machine?
Mealy and Moore fashions are the basic models of country machines. A state device which makes use of only Entry Actions, so that its output depends on the state, is called a Moore version. A kingdom system which makes use of handiest Input Actions, in order that the output relies upon at the state and additionally on inputs, is referred to as a Mealy model. The models selected will affect a design however there aren't any widespread symptoms as to which model is better. Choice of a version depends on the software, execution way (as an example, hardware structures are normally exceptional realized as Moore fashions) and private options of a clothier or programmer
Mealy system has outputs that depend upon the state and input (hence, the FSM has the output written on edges) Moore machine has outputs that rely on country simplest (consequently, the FSM has the output written inside the kingdom itself.
Adv and Disadv
In Mealy as the output variable is a characteristic both input and kingdom, adjustments of kingdom of the country variables can be not on time with admire to adjustments of sign stage within the enter variables, there are opportunities of system defects acting in the output variables. Moore overcomes system defects as output dependent on most effective states and not the enter signal level.
All of the principles can be implemented to Mooremodel state machines because any Moore state system can be implemented as a Mealy state gadget, even though the communicate isn't always proper.
Moore machine: the outputs are properties of states themselves…
which means that you get the output after the gadget reaches a particular kingdom, or to get a few output your gadget has to be taken to a nation which presents you the output.The outputs are held until you visit a few other country Mealy device:
Mealy machines come up with outputs immediately, that is without delay upon receiving enter, but the output isn't always held after that clock cycle.
Question nine. Difference Between Onehot And Binary Encoding?
Common classifications used to describe the state encoding of an FSM are Binary (or noticeably encoded) and One warm.
A binaryencoded FSM design only requires as many flipflops as are needed to uniquely encode the wide variety of states within the kingdom system. The real wide variety of flipflops required is same to the ceiling of the logbase2 of the number of states within the FSM.
A onehot FSM layout requires a flipflop for every state in the design and only one flipflop (the flipflop representing the contemporary or “hot” kingdom) is set at a time in a one warm FSM layout. For a nation device with 916 states, a binary FSM handiest calls for 4 flipflops even as a onehot FSM calls for a flipflop for every country within the layout FPGA companies regularly propose the use of a onehot kingdom encoding style due to the fact flipflops are ample in an FPGA and the combinational logic required to put in force a onehot FSM design is normally smaller than most binary encoding patterns. Since FPGA overall performance is typically related to the combinational logic size of the FPGA layout, onehot FSMs usually run quicker than a binary encoded FSM with larger combinational common sense blocks
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Question 10. How To Achieve 180 Degree Exact Phase Shift?
Never tell the usage of inverter
a) dcm’s an in-built resource in maximum of fpga can be configured to get 180 degree phase shift.
B) Bufgds that is differential signaling buffers that are additionally inbuilt aid of most of FPGA can be used.
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Question eleven. What Is Significance Of Ras And Cas In Sdram?
SDRAM receives its cope with command in cope with words.
It makes use of a multiplex scheme to store enter pins. The first deal with phrase is latched into the DRAM chip with the row deal with strobe (RAS).
Following the RAS command is the column deal with strobe (CAS) for latching the second address word.
Shortly after the RAS and CAS strobes, the stored facts is legitimate for analyzing.
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Question 12. Tell Some Of Applications Of Buffer?
They are used to introduce small delays
They are used to put off go talk prompted because of inter electrode capacitance because of near routing.
They are used to support excessive fanout,eg:bufg
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Question thirteen. Implement An And Gate Using Mux?
This is the basic query that many interviewers ask. For and gate, supply one input as select line,incase if u r giving b as choose line, connect one enter to common sense ‘zero’ and different enter to a.
Question 14. What Will Happen If Contents Of Register Are Shifter Left, Right?
It is widely recognized that during left shift all bits will be shifted left and LSB might be appended with zero and in proper shift all bits might be shifted proper and MSB could be appended with zero this is a trustworthy answer What is anticipated is in a left shift price receives Multiplied by way of 2 eg:remember 0000_1110=14 a left shift will make it 0001_110=28, it the equal style right shift will Divide the value via 2.
Question 15. What Is A Multiplexer?
A multiplexer is a combinational circuit which selects considered one of many enter indicators and directs to the only output.
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Question sixteen. What Is A Ring Counter?
A ring counter is a form of counter composed of a circular shift register. The output of the remaining shift check in is fed to the input of the primary sign in. For instance, in a four-register counter, with preliminary check in values of 1100, the repeating sample is: 1100, 0110, 0011, 1001, 1100, so on.
Question 17. Compare And Contrast Synchronous And Asynchronous Reset?
Synchronous reset good judgment will synthesize to smaller flip-flops, especially if the reset is gated with the common sense producing the d-input. But in one of these case, the combinational good judgment gate rely grows, so the general gate be counted savings may not be that huge. The clock works as a filter out for small reset system defects; but, if these glitches arise near the active clock area, the Flip-flop ought to move metastable. In some designs, the reset should be generated with the aid of a fixed of internal conditions. A synchronous reset is recommended for those forms of designs as it will filter out the common sense equation system faults among clock.
Problem with synchronous resets is that the synthesis device can't without difficulty distinguish the reset signal from any other facts signal. Synchronous resets may additionally want a pulse stretcher to assure a reset pulse width extensive enough to ensure reset is present at some stage in an active edge of the clock, if you have a gated clock to shop energy, the clock may be disabled coincident with the statement of reset. Only an asynchronous reset will work in this situation, because the reset is probably eliminated previous to the resumption of the clock. Designs which are pushing the restriction for facts course timing, can't have the funds for to have delivered gates and extra net delays inside the records direction because of common sense inserted to address synchronous resets.
Asynchronous reset: The principal trouble with asynchronous resets is the reset launch, additionally referred to as reset elimination. Using an asynchronous reset, the clothier is assured no longer to have the reset delivered to the statistics course. Another advantage favoring asynchronous resets is that the circuit can be reset with or without a clock present. Ensure that the discharge of the reset can occur inside one clock length else if the release of the reset occurred on or close to a clock facet then turn-flops may go into metastable state.
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Question 18. What Is A Johnson Counter?
Johnson counter connects the supplement of the output of the last shift sign up to its input and circulates a stream of ones accompanied by zeros around the ring. For instance, in a 4-register counter, the repeating sample is: 0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001, so on.
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Question 19. What Are The Differences Between A Flip-flop And A Latch?
Flip-flops are area-sensitive gadgets where as latches are degree sensitive devices.
Flip-flops are proof against system defects in which are latches are sensitive to system faults.
Latches require less wide variety of gates (and consequently less strength) than turn-flops.
Latches are quicker than turn-flops.
Question 20. What Is The Difference Between Mealy And Moore Fsm?
Mealy FSM makes use of simplest input movements, i.E. Output depends on input and country. The use of a Mealy FSM leads regularly to a reduction of the variety of states.
Moore FSM makes use of handiest access actions, i.E. Output relies upon only at the state. The advantage of the Moore model is a simplification of the behavior.
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Question 21. What Are Various Types Of State Encoding Techniques? Explain Them?
One-Hot encoding: Each country is represented by means of a chunk flip-flop). If there are 4 states then it requires four bits (4 flip-flops) to represent the current country. The valid kingdom values are a thousand, 0100, 0010, and 0001. If the cost is 0100, then it manner 2nd nation is the modern state.
One-Cold encoding: Same as one-warm encoding besides that '0' is the valid value. If there are four states then it requires four bits (4 flip-flops) to symbolize the cutting-edge state. The valid kingdom values are 0111, 1011, 1101, and 1110.
Binary encoding: Each nation is represented by a binary code. A FSM having '2 energy N' states calls for simplest N turn-flops.
Gray encoding: Each kingdom is represented by way of a Gray code. A FSM having '2 electricity N' states calls for only N turn-flops.
Question 22. Define Clock Skew , Negative Clock Skew, Positive Clock Skew?
Clock skew is a phenomenon in synchronous circuits wherein the clock signal (despatched from the clock circuit) arrives at exclusive additives at extraordinary times. This may be caused by many various things, consisting of wire-interconnect length, temperature variations, version in intermediate devices, capacitive coupling, fabric imperfections, and differences in input capacitance at the clock inputs of gadgets using the clock.
There are two types of clock skew: negative skew and high-quality skew. Positive skew takes place when the clock reaches the receiving register later than it reaches the check in sending records to the receiving register. Negative skew is the opposite: the receiving sign up receives the clock earlier than the sending sign in.
Question 23. Define Metastability?
If there are setup and maintain time violations in any sequential circuit, it enters a nation wherein its output is unpredictable, this kingdom is known as metastable state or quasi solid state, on the end of metastable nation, the flip-flop settles right down to both common sense excessive or common sense low. This whole manner is called metastability.
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Question 24. What Are Set Up Time And Hold Time Constraints?
Set up time is the amount of time earlier than the clock facet that the enter sign wishes to be stable to assure it's far established well on the clock area.
Hold time is the quantity of time after the clock facet that same enter signal must be held before converting it to make sure it is sensed properly on the clock facet.
Whenever there are setup and hold time violations in any flip-flop, it enters a country in which its output is unpredictable, that's referred to as as metastable state or quasi solid country. At the cease of metastable nation, the turn-flop settles all the way down to either common sense high or good judgment low. This complete method is referred to as metastability.
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Question 25. Expand The Following: Pla, Pal, Cpld, Fpga?
PLA - Programmable Logic Array
PAL - Programmable Array Logic
CPLD - Complex Programmable Logic Device
FPGA - Field-Programmable Gate Array
Question 26. What Are Pla And Pal? Give The Differences Between Them?
Programmable Logic Array is a programmable device used to put in force combinational good judgment circuits. The PLA has a fixed of programmable AND planes, which link to a fixed of programmable OR planes, which could then be conditionally complemented to supply an output.
PAL is programmable array good judgment, like PLA, it additionally has a wide, programmable AND plane. Unlike a PLA, the OR aircraft is fixed, proscribing the range of phrases that may be ORed together.
Due to fixed OR aircraft PAL lets in greater space, that is used for other primary logic gadgets, inclusive of multiplexers, distinctive-ORs, and latches. Most importantly, clocked elements, usually turn-flops, may be covered in PALs. PALs are also extremely rapid.
Question 27. What Is Lut?
LUT - Look-Up Table. An n-bit look-up table may be implemented with a multiplexer whose choose traces are the inputs of the LUT and whose inputs are constants. An n-bit LUT can encode any n-input Boolean function by using modeling such capabilities as truth tables. This is an efficient manner of encoding Boolean good judgment capabilities, and LUTs with 4-6 bits of enter are in fact the important thing thing of present day FPGAs.
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Question 28. What Is The Significance Of Fpgas In Modern Day Electronics? (programs Of Fpga.)
ASIC prototyping: Due to excessive price of ASIC chips, the common sense of the software is first proven through dumping HDL code in a FPGA. This allows for quicker and cheaper checking out. Once the common sense is tested then they may be made into ASICs.
Very beneficial in programs that may employ the big parallelism provided via their architecture. Example: code breaking, especially brute-force assault, of cryptographic algorithms.
FPGAs are sued for computational kernels which include FFT or Convolution in place of a microprocessor.
Applications consist of virtual sign processing, software program-described radio, aerospace and protection structures, scientific imaging, laptop imaginative and prescient, speech recognition, cryptography, bio-informatics, pc hardware emulation and a developing range of other regions.
Question 29. Arrange The Following In The Increasing Order Of Their Complexity: Fpga,pla,cpld,buddy?
Increasing order of complexity: PLA, PAL, CPLD, FPGA.