Question 1. What Is Fpga ?
A area-programmable gate array is a semiconductor tool containing programmable logic additives known as "logic blocks", and programmable interconnects. Logic blocks may be programmed to perform the characteristic of primary logic gates such as AND, and XOR, or greater complicated combinational functions which includes decoders or mathematical capabilities. In most FPGAs, the logic blocks also encompass memory elements, which can be simple flip-flops or more whole blocks of reminiscence. A hierarchy of programmable interconnects permits common sense blocks to be interconnected as needed by means of the machine dressmaker, somewhat like a one-chip programmable breadboard.
Logic blocks and interconnects may be programmed through the client or dressmaker, after the FPGA is manufactured, to put into effect any logical feature—consequently the name "discipline-programmable". FPGAs are normally slower than their software-particular integrated circuit (ASIC) opposite numbers, cannot manage as complicated a design, and draw extra electricity (for any given semiconductor manner). But their benefits include a shorter time to marketplace, capacity to re-application in the field to fix bugs, and decrease non-recurring engineering prices. Vendors can sell less expensive, less flexible versions in their FPGAs which can not be modified after the layout is committed. The designs are evolved on everyday FPGAs after which migrated into a fixed version that greater resembles an ASIC.
Question 2. What Logic Is Inferred When There Are Multiple Assign Statements Targeting The Same Wire?
It is illegal to specify multiple assign statements to the same cord in a synthesizable code that will become an output port of the module. The synthesis equipment deliver a syntax errors that a net is being pushed through more than one supply. However, it's far legal to force a 3-country wire by way of multiple assign statements.
Basic Simulation Interview Questions
Question three. What Is Minimum And Maximum Frequency Of Dcm In Spartan-three Series Fpga?
Spartan series dcm’s have a minimal frequency of 24 MHZ and a most of 248
Question 4. Suppose For A Piece Of Code Equivalent Gate Count Is 600 And For Another Code Equivalent Gate Count Is 50,000 Will The Size Of Bitmap Change?In Other Words Will Size Of Bitmap Change It Gate Count Change?
The size of bitmap is irrespective of resource utilization, it's far usually the identical,for Spartan xc3s5000 it is 1.56MB and could in no way change.
Question 5. What Are Different Types Of Fpga Programming Modes?What Are You Currently Using ?How To Change From One To Another?
Before powering at the FPGA, configuration records is saved externally in a PROM or some other nonvolatile medium both on or off the board. After making use of electricity, the configuration statistics is written to the FPGA using any of five one of a kind modes: Master Parallel, Slave Parallel, Master Serial, Slave Serial, and Boundary Scan (JTAG). The Master and Slave Parallel modes
Mode deciding on pins can be set to pick out the mode, refer facts sheet for similarly information.
Verilog Interview Questions
Question 6. Can You List Out Some Of Synthesizable And Non Synthesizable Constructs?
now not synthesizable
unnoticed for synthesis.
overlooked for synthesis.
no longer supported.
Real information kind now not supported.
Time information type no longer supported.
Force and launch
Force and launch of facts types now not supported.
Use nonblocking assignments to get identical impact.
Consumer defined primitives
Only gate level primitives are supported.
assign,for loop,Gate Level Primitives,repeat with regular value...
Question 7. Can You Explain What Struck At Zero Means?
These caught-at issues will appear in ASIC. Some times, the nodes will completely tie to 1 or zero because of a few fault. To keep away from that, we want to offer testability in RTL. If it's far permanently 1 it's far known as caught-at-1 If it's miles completely 0 it's far known as caught-at-0.
Wireless Interview Questions
Question 8. Difference Between Fpga And Cpld?
SRAM based totally era.
Segmented connection between factors.
Usually used for complex common sense circuits.
Must be reprogrammed once the strength is off.
Flash or EPROM based totally technology.
Continuous connection between elements.
Usually used for simpler or moderately complicated logic circuits.
Need no longer be reprogrammed as soon as the strength is off.
Question nine. What Are Dcm's?Why They Are Used?
Digital clock supervisor (DCM) is a completely virtual manage system that makes use of feedback to maintain clock signal characteristics with ahigh degree of precision despite regular variations in working temperature and voltage.
That is clock output of DCM is strong over huge range of temperature and voltage , and also skew associated with DCM is minimum and all stages of enter clock may be received . The output of DCM coming shape worldwide buffer can take care of more load.
Aerospace Interview Questions
Question 10. Can A Clb Configured As Ram?
YES. The reminiscence task is a clocked behavioral venture, Reads from the reminiscence are asynchronous, And all the cope with strains are shared by means of the read and write statements.
Question 11. What Is Purpose Of A Constraint File What Is Its Extension?
The UCF record is an ASCII document specifying constraints at the logical layout. You create this file and enter your constraints within the document with a text editor. You also can use the Xilinx Constraints Editor to create constraints inside a UCF(extention) report. These constraints have an effect on how the logical layout is applied within the goal device. You can use the record to override constraints exact at some stage in layout entry.
System Verilog Interview Questions
Question 12. How Many Global Buffers Are There In Your Current Fpga,what Is Their Significance?
There are eight of them in xc3s5000
An external clock source enters the FPGA the use of a Global Clock Input Buffer (IBUFG), which at once accesses the global clock network or an Input Buffer (IBUF). Clock indicators within the FPGA drive a international clock internet the use of a Global Clock Multiplexer Buffer (BUFGMUX). The worldwide clock internet connects at once to the CLKIN enter.
Basic Simulation Interview Questions
Question thirteen. Why Is Map-timing Option Used?
Timing-driven packing and location is suggested to improve layout performance, timing, and packing for relatively utilized designs.
Question 14. What Are Different Types Of Timing Verifications?
The layout is simulated in complete timing mode.
Not all opportunities tested as it is dependent on the input check vectors.
Simulations in complete timing mode are slow and require a variety of memory.
Best approach to check asynchronous interfaces or interfaces among one-of-a-kind timing domain names.
The delays over all paths are introduced up.
All possibilities, together with fake paths, established without the want for take a look at vectors.
Much faster than simulations, hours in preference to days.
Not exact with asynchronous interfaces or interfaces between special timing domains.
Question 15. Compare Pll & Dll ?
PLLs have disadvantages that make their use in high-velocity designs intricate, specifically whilst each high performance and high reliability are required.
The PLL voltage-managed oscillator (VCO) is the greatest supply of troubles. Variations in temperature, supply voltage, and manufacturing method affect the steadiness and running overall performance of PLLs.
DLLs, but, are resistant to those troubles. A DLL in its best shape inserts a variable put off line between the outside clock and the inner clock. The clock tree distributes the clock to all registers after which again to the feedback pin of the DLL.
The manipulate circuit of the DLL adjusts the delays so that the rising edges of the comments clock align with the enter clock. Once the rims of the clocks are aligned, the DLL is locked, and each the input buffer postpone and the clock skew are decreased to 0.
jitter overall performance.
VHDL Interview Questions
Question sixteen. Given Two Asics. One Has Setup Violation And The Other Has Hold Violation. How Can They Be Made To Work Together Without Modifying The Design?
Slow the clock down on the only with setup violations. And add redundant good judgment within the route where you have maintain violations.
Question 17. Suggest Some Ways To Increase Clock Frequency?
Check crucial course and optimize it.
Add more timing constraints (over constrain).
Pipeline the structure to the max viable quantity preserving in thoughts latency req's.
XLink Interview Questions
Question 18. What Is The Purpose Of Drc?
DRC is used to check whether or not the specific schematic and corresponding layout(especially the masks sets concerned) cater to a pre-described rule set depending at the era used to layout. They are parameters set aside by means of the worried semiconductor manufacturer with admire to how the masks must be placed , connected , routed retaining in thoughts that versions inside the fab technique does no longer effect normal capability. It generally denotes the minimal allowable configuration.
Verilog Interview Questions
Question 19. What Is Lvs And Why Do We Do That. What Is The Difference Between Lvs And Drc?
The layout need to be drawn consistent with certain strict design guidelines. DRC allows in format of the designs by means of checking if the layout is abide via the ones guidelines.
After the layout is entire we extract the netlist. LVS compares the netlist extracted from the layout with the schematic to make certain that the layout is an same healthy to the cellular schematic.
Question 20. What Is Dft ?
DFT manner design for testability. 'Design for Test or Testability' - a methodology that guarantees a layout works properly after manufacturing, which later facilitates the failure analysis and fake product/piece detection
Other than the purposeful common sense,you want to feature some DFT good judgment in your layout.This will help you in trying out the chip for manufacturing defects after it come from fab. Scan,MBIST,LBIST,IDDQ testing and many others are all a part of this. (this is a hot field and with lots of opportunities)
ASIC Interview Questions
Question 21. There Are Two Major Fpga Companies: Xilinx And Altera. Xilinx Tends To Promote Its Hard Processor Cores And Altera Tends To Promote Its Soft Processor Cores. What Is The Difference Between A Hard Processor Core And A Soft Processor Core?
A tough processor middle is a pre-designed block that is embedded onto the device. In the Xilinx Virtex II-Pro, a number of the common sense blocks were removed, and the distance that turned into used for these logic blocks is used to put in force a processor. The Altera Nios, on the other hand, is a layout that may be compiled to the everyday FPGA logic.
Question 22. When Are Dft And Formal Verification Used?
production defects like stuck at "zero" or "1".
Take a look at for set of guidelines observed in the course of the initial design stage.
Verification of the operation of the design, i.E, to look if the design follows spec.
Gate netlist == RTL ?
The use of mathematics and statistical analysis to check for equivalence.
Question 23. What Is Synthesis?
Synthesis is the degree inside the design go with the flow which is worried with translating your Verilog code into gates - and that's placing it very certainly! First of all, the Verilog have to be written in a specific manner for the synthesis tool which you are the usage of. Of path, a synthesis tool doesn't honestly produce gates - it'll output a netlist of the design which you have synthesised that represents the chip which can be fabricated thru an ASIC or FPGA dealer.
Question 24. We Need To Sample An Input Or Output Something At Different Rates, But I Need To Vary The Rate? What's A Clean Way To Do This?
Many, many problems have this form of variable charge requirement, yet we are commonly limited with a constant clock frequency. One trick is to enforce a digital NCO (Numerically Controlled Oscillator). An NCO is really very simple and, at the same time as it's far maximum obviously understood as hardware, it also can be constructed in software program. The NCO, quite without a doubt, is an accumulator where you preserve including a set value on every clock (e.G. At a constant clock frequency). When the NCO "wraps", you sample your input or do your action.
By adjusting the value brought to the accumulator each clock, you finely song the AVERAGE frequency of that wrap event. Now - you may have found out that the wrapping event may have lots of jitter on it. True, but you could use the wrap to increment yet any other counter where each extra Divide-by-2 bit reduces this jitter. The DDS is a related technique. I have examples showing each an NCOs and a DDS in my File Archive. This is hard to understand at the beginning, however fantastically effective as soon as you have it for your bag of tricks. NCOs additionally relate to digital PLLs, Timing Recovery, TDMA and different "variable fee" phenomena
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