Question 1. Explain What Is Transmission Gate-based D-latch?

Answer :

The Transmission-Gate input is hooked up to the D_LATCH facts input (D), the manipulate input to the Transmission-Gate is connected to the D_LATCH permit enter (EN) and the Transmission-Gate output is the D_LATCH output (Q).

Question 2. How To Detect Sequence Of "1101" Arriving Serially From Signal Line?

Answer :

Sequence detector : A sequence detector offers an output of one on detecting the given collection else the output is 0.

Ex : if the given collection to be detected is 111

and input circulate is 1 1 zero 1 1 1 0 zero 1 zero 1 1 1 1 1

the output must be zero zero zero zero 0 1 0 zero zero zero 0 zero 1 1 1.

Soln:

One of the special viable approaches to discover a series is the use of a Mealy type FSM.

Using the subsequent desk the State machine can be designed.

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Question 3. Which Are The Two Ways Of Converting A Two Input Nand Gate To An Inverter?

Answer :

Short the two inputs of the nand gate and provide the same enter to the commonplace wire,the nand gate works as an inverter.

One way is shorting the 2 inputs of the NAND gate and passing the enter.

Truth table:

A B output

1 1 zero

0 0 1

The second way is passing the input to simplest one input(say A) of the NAND gate.Since the other input(say B) is floating, it's far always logic one.

Truth table:

A B output

1 1 zero

0 1 1

Question 4. How To Design A Divide-by-three Sequential Circuit With 50% Duty Circle?

Answer :

Take a counter with 3 f/f's that is to say with 6 states(2*3) now double the i/p clock frequency to the counter the o/p of the 3rd f/f is divide by means of 6 of the i/p with 50% duty cycle so successfully u got divide by means of three freq with 50% obligation cycle.

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Question five. What Are The Different Adder Circuits You Studied?

Answer :

Adders are commonly of 5 kinds:

1) Ripple Carry Adder: The Ripple bring adder(RCA) includes a building block named Half Adder(HA) which is cascaded to shape a Full Adder(FA). These building blocks HAs and FAs are also the constructing blocks of all sorts of adders.The n complete adders are cascaded to form n bit RCA.

The full adder has three input pins(enter Ai,input Bi,carryin Ci) and output pins(Sum and Ci+1).Its equations are:

Sum=Ai^Bi^Ci

Ci+1=Ai.Bi+Bi.Ci+Ai.Ci

2)Carry Lookahead Adder: The Carry Lookahead Adder(CLA) reduces the put off as that during RCA. Let

Gi=Ai.Bi, and Pi=Ai^Bi, then Ci+1=Gi+Pi.Ci.

The expressions for Sum and Ci+1 is then described absolutely in terms of input pins instead watch for enter carry to seem.

3)Carry Select Adder: The carry select adder uses duplicate modules for every combination of enter deliver(i.E. 1 and zero).The multiplexers then choose the appropriate sum and carry output in step with the carry output of the preceding levels.

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Question 6. What Are Set Up Time & Hold Time Constraints? What Do They Signify? Which One Is Critical For Estimating Maximum Clock Frequency Of A Circuit?

Answer :

Suppose your flip-flop is fantastic side prompted. Time for which information must be strong previous to wonderful side clock is called setup time constraint .

Time for which information should be strong after the high quality edge of clock is known as as hold time constraint.

If any of these constraints are violated then turn-flop will enter in meta solid nation, in which we can't determine the output of turn-flop.

There are equation:

Tcq + Tcomb> Tskew + Thold

Tcq + Tcomb<Tskew +T - Tsetup

Tcq is time postpone while data enters the turn-flop and data comes at output of turn flop.

Tcomb is the common sense delay among two turn flop.

Tskew is the put off of clock to flip flop: suppose there are flip flop ,if clock reaches first to source turn flop and then after some postpone to destination flip flop ,it's far advantageous skew and if vice versa then terrible skew.

So in case you take 2 eq you will see that setup time is the determining aspect of clock's term.

Question 7. Give A Circuit To Divide Frequency Of Clock Cycle By Two?

Answer :

You can divide the frequency of a clock by just enforcing T Flip flop.

Give clock as clock input and tie the T input to common sense 1.

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Question eight. How Do You Detect If Two eight-bit Signals Are Same?

Answer :

XOR each bits of A with B (for eg A[0] xor B[0] ) and so forth. The o/p of eight xor gates are then given as i/p to an 8-i/p nor gate. If o/p is 1 then A=B.

Question 9. Give Two Ways Of Converting A Two Input Nand Gate To An Inverter?

Answer :

One way is shorting the 2 inputs of the NAND gate and passing the enter.

Truth desk:

A B output

1 1 0

zero 0 1

The 2nd way is passing the input to only one input(say A) of the NAND gate.Since the other enter(say B) is floating, it's far constantly common sense one.

Fact table:

A B output

1 1 0

0 1 1

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Question 10. Design A Divide-by means of-3 Sequential Circuit With 50% Duty Circle?

Answer :

Take a smiths counter with 3 f/f's this is to say with 6 states(2*3) now double the i/p clock frequency to the counter the o/p of the third f/f is divide by using 6 of the i/p with 50% obligation cycle so successfully u got divide with the aid of three freq with 50% responsibility cycle

Question 11. Give The Truth Table For A Half Adder. Give A Gate Level Implementation Of The Same?

Answer :

TRUTH TABLE FOR HALF ADDER:

A B SUM CARRY

0 0 zero 0

zero 1 1 0

1 0 1 0

1 1 zero 1

IMPLEMENTATION:

For SUM, The two inputs A and B are given to XOR gate.

For Carry, The inputs A and B are given to AND gate.

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Question 12. How Do You Detect A Sequence Of "1101" Arriving Serially From A Signal Line?

Answer :

Sequence detector : A collection detector offers an output of 1 on detecting the given series else the output is 0.

Ex : if the given collection to be detected is 111

and input move is 1 1 zero 1 1 1 zero zero 1 zero 1 1 1 1 1

the output have to be 0 zero 0 0 zero 1 0 zero 0 zero 0 0 1 1 1.

Soln: One of the distinct feasible ways to come across a series is the use of a Mealy type FSM.

Using the following table the State system may be designed. Since the variety of bits in the series 1101 is 4 we've fourPS through the country X=0 X=1 0 S2/0

zero 0 S3 11 0 0 S4 110 zero

while in state S4 (PS),and enter(X) from the sequence is 1,the series "1101" has been detected as soon as and (to discover the subsequent kingdom pick out the longest "seq diagnosed by way of a state" column that fits a part of the sequence 1101--ie.,1 or 01 or 101 ....)the NS is S2 for the reason that collection detected by means of the country S2 is 1(in 1101- 01 or one hundred and one ,and so forth aren't present inside the seq identified by way of the country column ,)

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Question thirteen. Suppose You Have A Combinational Circuit Between Two Registers Driven By A Clock. What Will You Do If The Delay Of The Combinational Circuit Is Greater Than Your Clock Signal?

Answer :

Use the concept of check in-retiming.

Divide the whole combinatorial delay in segments such that for my part the delay is much less the clock length.

This will be completed by using placing a turn-flop inside the combinational path.

E.G,

clock duration --- five ns

total cominational delay ---- 7

then divide the 7ns route in direction of 4 or three (excellent effects are received if delays are same for both course i.E three.5ns) with the aid of putting a turn-flop in among.

Question 14. Draw A Transmission Gate-based totally D-latch?

Answer :

The Transmission-Gate's input is attached to the D_LATCH facts input (D), the manage enter to the Transmission-Gate is attached to the D_LATCH allow input (EN) and the Transmission-Gate output is the D_LATCH output (Q)